A Quaternary Decision Diagram Machine and the Optimization of Its Code

Abstract

We show the advantage of Quarternary Decision Diagrams (QDDs) in representing and evaluating logic functions. That is, we show how QDDs are used to implement QDD machines, which yield high-speed implementations. We compare QDD machines with binary decision diagram (BDD) machines, and show a speed improvement of 1.28- 2.02 times when QDDs are chosen. We consider 1-and 2- address BDD machines, and 3- and 4-address QDD machines, and we show a method to minimize the number of instructions.

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Document Details

Document Type
Technical Report
Publication Date
Jan 01, 2009
Accession Number
ADA548113

Entities

People

  • Hiroki Nakahara
  • Jon T. Butler
  • Munehiro Matsuura
  • Tsutomu Sasao
  • Yoshifumi Kawamura

Organizations

  • Naval Postgraduate School

Tags

DTIC Thesaurus Topics

  • Abstracts
  • Air Force
  • Algorithms
  • Computations
  • Computers
  • Education
  • Embedded Systems
  • Heuristic Methods
  • Information Operations
  • Instructions
  • Language
  • Optimization
  • Standards
  • Terminals
  • Test And Evaluation

Fields of Study

  • Computer science

Readers

  • Adaptive Control and Estimation with Uncertainty in Dynamic Systems.
  • Computer Engineering
  • Manufacturing Engineering.