Dense Heterogeneous Integration for InP Bi-CMOS Technology

Abstract

InP Bi-CMOS technology capable of wafer-scale device-level heterogeneous integration (HI) of InP HBTs and CMOS has been developed. With this technology, full simultaneous utilization of III-V device speed and CMOS circuit complexity is possible. Simple ICs and test structures have been fabricated, showing no significant CMOS or HBT degradation and high heterogeneous interconnect yield. The heterogeneously integrated differential amplifiers with record performance and HBTs with fT=400GHz were obtained. Thermal vias to the Si substrate provide sufficient heat path to lower HI HBT thermal resistances close to on-InP values. Resulting circuits maintain maximum CMOS integration density and HBT performance, while keeping the heterogeneous interconnect length below 5μm.

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Document Details

Document Type
Technical Report
Publication Date
May 01, 2009
Accession Number
ADA553253

Entities

People

  • D. A. Hitko
  • J. R. Duvall
  • J. S. Sewell
  • Jie Li
  • K. R. Elliiott
  • M. C. Montes
  • M. F. Boag-o'brien
  • P. R. Patterson
  • T. Hussain
  • Y. Royter

Organizations

  • Air Force Research Laboratory

Tags

DTIC Thesaurus Topics

  • Air Force Research Laboratories
  • Amplifiers
  • Compound Semiconductors
  • Degradation
  • Epitaxial Growth
  • Fabrication
  • Frequency
  • Heat Energy
  • Impedance
  • Materials
  • Resistance
  • Semiconductor Devices
  • Semiconductors
  • Standards
  • Substrates
  • Thermal Resistance
  • Voltage

Readers

  • Integrated Circuit Design and Technology.
  • Thermal Physics or Thermal Science.