Modeling SiO2 Ion Impurities Aging in Insulated Gate Power Devices Under Temperature and Voltage Stress

Abstract

This paper presents a formal computational methodology to explain how the oxide in semiconductors degrades over time and the dependence of oxide degradation on voltage and temperature stresses. The effects of aging are modeled and quantified by modification of the gate-source capacitance value. The model output is validated using experimental results of a thermally aged power semiconductor device.

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Document Details

Document Type
Technical Report
Publication Date
Oct 01, 2010
Accession Number
ADA562425

Entities

People

  • Antonio E. Ginart
  • Irfan N. Ali
  • Jose R. Celaya
  • Michael J. Roemer
  • Patrick W. Kalgren
  • Scott D. Poll

Tags

Communities of Interest

  • Advanced Electronics
  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Abstracts
  • Arrhenius Equation
  • Bipolar Junction Transistors
  • Capacitance
  • Degradation
  • Ecology
  • Electric Fields
  • Electronics
  • Fabrication
  • Failure Mode And Effect Analysis
  • High Temperature
  • Materials
  • Reliability Engineering
  • Semiconductor Devices
  • Semiconductors
  • Transistors
  • United States

Fields of Study

  • Engineering

Readers

  • Computational Modeling and Simulation
  • Polymer Science and Engineering.
  • Semiconductor Device Technology

Technology Areas

  • Microelectronics