Cache Hardware Approaches to Multiple Independent Levels of Security (MILS)

Abstract

The purpose of this research is to explore possible security vulnerabilities in the cache memory systems of modern multicore processors, and to develop the tools necessary for exploring such vulnerabilities, including a model that allows for the simulation of the vulnerability and for the implementation of possible solutions that defeat the effectiveness of the vulnerability.

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Document Details

Document Type
Technical Report
Publication Date
Oct 01, 2012
Accession Number
ADA568861

Entities

People

  • Robert Rinker

Organizations

  • University of Idaho

Tags

Communities of Interest

  • Advanced Electronics
  • Cyber

DTIC Thesaurus Topics

  • Air Force
  • Air Force Research Laboratories
  • Application-Specific Integrated Circuits
  • Central Processing Units
  • Communication Systems
  • Computer Programming
  • Computer Programs
  • Computer Science
  • Computers
  • Field Programmable Gate Arrays
  • Firmware
  • Instruction Set Architecture
  • Integrated Circuits
  • Intellectual Property
  • Operating Systems
  • Simulations
  • Very Large Scale Integration

Fields of Study

  • Computer science
  • Mathematics

Readers

  • Cybersecurity.
  • Parallel and Distributed Computing.