Frequency Agile Wideband Phase Lock Loops for RF-FPGAs
Abstract
This project develops phase locked loop (PLL) macros that use novel digital architectures to achieve a user configurable optimum balance between phase noise, frequency resolution, frequency switching time, and power consumption. The PLL macros are implemented in SiGe BiCMOS to take advantage of the good phase noise and power consumption attributes. The digital nature of the implementation facilitates easy porting to more aggressively scaled processes.
Document Details
- Document Type
- Technical Report
- Publication Date
- Mar 01, 2013
- Accession Number
- ADA578605
Entities
People
- Bert Sullam
- James H. Crawford
- Jeremy Popp
- Monte Mar
- Xiaoyin Yao
Organizations
- Boeing