Design Method for Numerical Function Generators Using Recursive Segmentation and EVBDDs
Abstract
Numerical function generators (NFGs) realize arithmetic functions, such as e(x), sin(pi x), and square root x, in hardware. They are used in applications where high-speed is essential, such as in digital signal or graphics applications. We introduce the edge-valued binary decision diagram (EVBDD) as a means of reducing the delay and memory requirements in NFGs. We also introduce a recursive segmentation algorithm, which divides the domain of the function to be realized into segments, where the given function is realized as a polynomial. This design reduces the size of the multiplier needed and thus reduces delay. It is also shown that an adder can be replaced by a set of 2-input AND gates, further reducing delay. We compare our results to NFGs designed with multi-terminal BDDs (MTBDDs). We show that EVBDDs yield a design that has, on the average, only 39% of the memory and 58% of the delay of NFGs designed using MTBDDs.
Document Details
- Document Type
- Technical Report
- Publication Date
- Dec 01, 2007
- Accession Number
- ADA596366
Entities
People
- Jon T. Butler
- Shinobu Nagayama
- Tsutomu Sasao
Organizations
- Naval Postgraduate School