Preliminary Study of Image Reconstruction Algorithm on a Digital Signal Processor

Abstract

With the advent of the parallel computing era, alternative processing solutions are examined for performance. Accelerators promise the potential to augment a system with only Intel or AMD central processing units. Specifically, digital signal processor (DSP) architecture is evaluated for computing image reconstruction algorithm. A Freescale DSP, drawing power in the range of 10 W, is considered for analysis. Software tools and programming techniques used during development are documented for the DSP platform. Preliminary results of the execution times are compared with graphics processing units and field programmable gate array technologies.

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Document Details

Document Type
Technical Report
Publication Date
Mar 01, 2014
Accession Number
ADA599165

Entities

People

  • Dale Shires
  • Daniel Rankin
  • Jeanine Cook
  • Song Park

Organizations

  • United States Army Research Laboratory

Tags

Communities of Interest

  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Algorithms
  • Central Processing Units
  • Circuits
  • Computer Programming
  • Computers
  • Computing System Architectures
  • Diagrams
  • Energy Consumption
  • Field Programmable Gate Arrays
  • Graphics
  • Graphics Processing Unit
  • Image Processing
  • Image Reconstruction
  • Integrated Circuits
  • Language
  • Parallel Computing
  • Parallel Processing

Fields of Study

  • Physics

Readers

  • Parallel and Distributed Computing.
  • Systems Analysis and Design