ABC: Aging-Based IC Configuration
Abstract
The continuously widening gap between the non-recurring engineering and recurring engineering costs of producing integrated circuit products in the past few decades gives high incentives to unauthorized cloning and reverse-engineering of ICs. Existing IC digital rights management schemes often demands high overhead in area, power, and performance, or require non-volatile storage. Our goal is to develop a novel intellectual property protection technique that offers universal protection to both ASICs and FPGAs from unauthorized manufacturing and reverse engineering. We present a proof-of-concept implementation of the basic elements of our techniques, as well as a case study of applying the anti-cloning technique to a nontrivial FPGA design. Furthermore, we present the use of benign hardware Trojans (BHTs) as a security measure for an embedded system with a software component and a hardware execution environment. Based on delay logic, process variation, and selective transistor aging, the BHT can be incorporated into an embedded system for the software and the hardware components to authenticate each other before functional execution. We demonstrate an implementation of such a BHT within an embedded system on a Xilinx Spartan-6 FPGA platform. Using the same platform we will also show that the BHT security measurement has a low to modest amount of performance overhead basing on the test results from a variety of synthetic and real world benchmarks.
Document Details
- Document Type
- Technical Report
- Publication Date
- Apr 01, 2014
- Accession Number
- ADA602909
Entities
People
- Miodrag Potkonjak
Organizations
- University of California, Los Angeles