Estimating Performance of Single Bus, Shared Memory Multiprocessors

Abstract

Given standard characteristics of processors and memory, we present two simple ways of estimating the performance of shared memory multiprocessors. At the cost of a few simple arithmetic operations, a computer designer can estimate the range of performance using our "4-point bound" model. If more accuracy is required, we show that a one page program can estimate performance within 3% of trace-driven simulation, while reducing software development time, disk space, and CPU time by orders of magnitude. To demonstrate the use of our models, an application to the SPUR multiprocessor design is presented.

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Document Details

Document Type
Technical Report
Publication Date
May 01, 1987
Accession Number
ADA604029

Entities

People

  • Garth Gibson

Organizations

  • University of California, Berkeley

Tags

Communities of Interest

  • Air Platforms

DTIC Thesaurus Topics

  • Accuracy
  • Computations
  • Computer Architecture
  • Computer Programming
  • Computer Science
  • Computers
  • Databases
  • Engineering
  • Mathematical Models
  • Models
  • Multiprocessors
  • Queueing Theory
  • Random Variables
  • Simulations
  • Simulators
  • Software Development
  • Standards

Fields of Study

  • Computer science

Readers

  • Life Cycle Cost Analysis
  • Parallel and Distributed Computing.

Technology Areas

  • Space