Multiple-Valued PLA Minimization by Concurrent Multiple and Mixed Simulated Annealing

Abstract

We analyze simulated annealing applied to multiple-valued programmable logic array (MVL PLA) design. Of specific interest is the use of parallel processors. We consider the use of loosely-coupled, coarse-grained parallel systems, and study the relationship between the quality of the solution and computation time, on the one hand, and simulated annealing parameters, start temperature, cooling rate, etc., on the other. We also investigate simulated annealing where there is a mixture of move types. The mixed move approach provides improvement in both the number of product terms and computation time.

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Document Details

Document Type
Technical Report
Publication Date
May 01, 1993
Accession Number
ADA605412

Entities

People

  • Cem Yildirim
  • Chyan Yang
  • Jon T. Butler

Organizations

  • Naval Postgraduate School

Tags

Communities of Interest

  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Abstracts
  • Algorithms
  • Annealing
  • Computations
  • Computer Programming
  • Computers
  • Governments
  • Information Operations
  • Mathematical Analysis
  • Mathematics
  • Military Research
  • Multithreading
  • Operating Systems
  • Probability
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