Multiple-Valued Logic Minimization for PLA Synthesis

Abstract

Multiple-valued logic minimization is an important technique for reducing the area required by a Programmable Logic Array (PLA). This report describes both heuristic and exact algorithms for solving the multiple-valued logic minimization problem. These algorithms have been implemented in a C program called Espresso-MV.

Open PDF

Document Details

Document Type
Technical Report
Publication Date
Jun 05, 1986
Accession Number
ADA606736

Entities

People

  • Richard L. Rudell

Organizations

  • University of California, Berkeley

Tags

Communities of Interest

  • Advanced Electronics
  • Air Platforms
  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Algorithms
  • Boolean Algebra
  • Coding
  • Computer Logic
  • Computer Programming
  • Computer Science
  • Computers
  • Electrical Engineering
  • Language
  • Logic
  • Notation
  • Operating Systems
  • Optimization
  • Standards
  • Symbols
  • Test Sets
  • Two Dimensional

Readers

  • Adaptive Control and Estimation with Uncertainty in Dynamic Systems.
  • Computer Programming and Software Development.