The Design of Current Mode CMOS Multiple-Valued Circuits

Abstract

We propose an algorithm for the design of multiple-valued current-mode CMOS logic (CMCL) circuits that is based on the cost-table technique. The algorithm is a heuristic search technique (AO* algorithm) applied to an AND-OR tree. It is significantly faster than Exhaustive Search while providing realizations that are almost as good. A new cost-table is also proposed that results in better realizations than obtained with a previous cost-table.

Open PDF

Document Details

Document Type
Technical Report
Publication Date
Jan 01, 1991
Accession Number
ADA608087

Entities

People

  • Jon T. Butler
  • Young-hoon Chang

Organizations

  • Naval Postgraduate School

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Abstracts
  • Algorithms
  • Charge Coupled Devices
  • Circuits
  • Cost Estimates
  • Costs
  • Decomposition
  • Detectors
  • Digital Images
  • Engineering
  • Generators
  • Information Operations
  • Logic
  • Logic Gates
  • Multiplication Factor
  • Numbers
  • Transistors

Fields of Study

  • Computer science

Readers

  • Applied Combinatorial Optimization and Logic Circuit Design.
  • Electrical Engineering