TLB for Free: In-Cache Address Translation for a Multiprocessor Workstation

Abstract

In the design of SPUR, a high-performance multiprocessor workstation, the need for large "snooping" caches suggests a new approach to virtual address translation. By performing this translation in each processor's virtual cache, the need for separate translation lookaside buffers is eliminated. Trace-driven simulations show that normal cache behavior is only minimally effected, and that unless an extremely large and complex TLB were built, using a separate device would actually reduce system performance.

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Document Details

Document Type
Technical Report
Publication Date
May 13, 1985
Accession Number
ADA611687

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  • Scott A. Ritchie

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  • University of California, Berkeley

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