Transistor Sizing

Abstract

Several methods of choosing appropriate sizes for transistors in a VLSI schematic to meet a specified delay criteria are considered. Simulated annealing and heuristic techniques are investigated. MOST is a Prolog program which makes use of information provided by the PTA timing analyzer to implement these various approaches. Both MOST and PTA are written entirely in (interpreted) Prolog; nonetheless, performance gains of over 50% as compared to an unsized circuit can be realized in a few minutes of CPU time. Using a simple RC timing model, heuristics are found to be more efficient than simulated annealing.

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Document Details

Document Type
Technical Report
Publication Date
Feb 01, 1986
Accession Number
ADA611783

Entities

People

  • Jonathan Pincus

Organizations

  • University of California, Berkeley

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Acceptance Tests
  • Accuracy
  • Algorithms
  • Analyzers
  • Annealing
  • California
  • Circuit Analysis
  • Circuits
  • Computations
  • Computer Programs
  • Computer Science
  • Heuristic Methods
  • Language
  • Logic Gates
  • Resistance
  • Statistics
  • Transistors

Readers

  • Government and Public Administration Law.
  • Integrated Circuit Design and Technology.
  • Operations Research