Cell Design in Prolog

Abstract

Automatic synthesis of CMOS cells is considered in the programming idiom of Prolog. Cells are specified at the boolean level using Prolog structures and a layout of the cell is generated at the CIF (Caltech Intermediate Format) level. A set of Prolog programs has been developed for this purpose. A three pass approach has been taken. The first pass takes boolean equations and transforms it into a net-list of transistors corresponding to static CMOS design style. The second pass (implemented by Rick Mcgeer) takes the transistor net-list and lays it out on a virtual grid in the style of a Gate Matrix. The third pass takes the sticks layout on the virtual grid and compacts it onto a lambda grid to produce CIF code. A few test cells have been passed through this cell synthesizer. Example cases include an exclusive-nor gate, a cross-coupled nand gate pair, a hand laid out exclusive-nor gate passed through the compactor only.

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Document Details

Document Type
Technical Report
Publication Date
Feb 25, 1986
Accession Number
ADA619311

Entities

People

  • Ashar A. Butt

Organizations

  • University of California, Berkeley

Tags

Communities of Interest

  • Advanced Electronics
  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Automatic
  • Circuits
  • Compilers
  • Computer Programming
  • Computer Programs
  • Computer Science
  • Computers
  • Computing System Architectures
  • Databases
  • Electrical Circuits
  • Equations
  • Instruction Set Architecture
  • Language
  • Nand Gates
  • Networks
  • Operating Systems
  • Transistors

Fields of Study

  • Engineering

Readers

  • Database Systems and Applications
  • Graph Algorithms and Convex Optimization.
  • Integrated Circuit Design and Technology.