Functional Specification and Simulation of a Floating Point Co-Processor for SPUR

Abstract

This report describes the internal organization of the SPUR floating point chip. The primary representation of the FPU microarchitecture is its functional level executable hardware description. This description serves as the primary chip design verification tool at both the functional and the layout levels. The text of this paper gives the operation sequence for the chip's instructions and details its datapath and control structures.

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Document Details

Document Type
Technical Report
Publication Date
Aug 01, 1986
Accession Number
ADA619390

Entities

People

  • Glenn D. Adams

Organizations

  • University of California, Berkeley

Tags

Communities of Interest

  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Abstracts
  • Arithmetic Units
  • Coding
  • Computer Science
  • Computing System Architectures
  • Data Transmission
  • Decoding
  • Detection
  • Floating Point Operations
  • Instructions
  • Language
  • Microarchitecture
  • Sequences
  • Simulations
  • Simulators
  • Standards
  • Verification

Fields of Study

  • Computer science
  • Engineering

Readers

  • Parallel and Distributed Computing.
  • Software Engineering