Floating Point Multiply-Add-Subtract Implementation

Abstract

A floating point multiply and addition/subtraction implementation is provided. Two operands are received in a standard floating point format with a code selecting a mathematic operation from addition, subtraction, and multiplication. Result mantissas and exponents are calculated simultaneously for all operations. The implementation simplifies computation of a result mantissa by dropping the least significant bits of the operands before computing the result. Underflow and overflow errors are shown by two extra bits in the exponent portion of the result. The mantissa result and the exponent result are selected by providing the operation code to a mantissa multiplexer and an exponent multiplexer. The selected mantissa and exponent are combined as output.

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Document Details

Document Type
Technical Report
Publication Date
Nov 07, 2014
Accession Number
ADA626736

Entities

People

  • Makia Powell

Organizations

  • Naval Undersea Warfare Center

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Application-Specific Integrated Circuits
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  • Circuits
  • Computations
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  • Digital Computers
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Fields of Study

  • Physics

Readers

  • Computer Programming and Software Development.