Hardware Acceleration of Sparse Cognitive Algorithms

Abstract

Hardware accelerators were designed for both the Sparsey and Numenta HTM cortical algorithms. Two versions were designed -- a programmable 65 nm SIMD version with Processor in Memory (PiM) extensions and a 65 nm ASIC version. They were compared against a 28 nm GPU baseline using the KTH video action recognition benchmark. Performance/power improvement over the GPU were (Sparsey) SIMD with PiM: 1490; ASIC: 1300; and (HTM) SIMD with PiM: 537; ASIC: 47,100.

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Document Details

Document Type
Technical Report
Publication Date
May 01, 2016
Accession Number
ADA631951

Entities

People

  • Joshua Schabel
  • Lee Baker
  • Paul D Franzon
  • Sumon Dey
  • Weifu Li

Organizations

  • North Carolina State University

Tags

Communities of Interest

  • Advanced Electronics
  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Air Force
  • Air Force Research Laboratories
  • Algorithms
  • Application-Specific Integrated Circuits
  • Central Processing Units
  • Complementary Metal-Oxide Semiconductors
  • Computational Science
  • Data Transmission
  • Digital Communications
  • Graphics Processing Unit
  • Instruction Set Architecture
  • Integrated Circuits
  • Kernel Functions
  • Neural Networks
  • Parallel Computing
  • Simulators
  • Three Dimensional

Readers

  • Integrated Circuit Design and Technology.
  • Nanoscale Plasmonic Nanotechnology
  • Research Science/Academic Research