Multi-SIB iWarp Array Configuration

Abstract

This document describes how to incorporate multiple SUN Interface Boards into an Intel iWarp parallel processing array. The described procedure was originally developed at Carnegie-Mellon University, and was applied to a 64-cell iWarp array at NUWC/NL. The addition of multiple SIBs significantly improves the input/output capacity of the array.

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Document Details

Document Type
Technical Report
Publication Date
Aug 22, 1994
Accession Number
ADA640520

Entities

People

  • W. R. Bernecky

Organizations

  • Naval Undersea Warfare Center

Tags

Communities of Interest

  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Abstracts
  • Communication Networks
  • Computer Programming
  • Computers
  • Connectors
  • Device Drivers
  • Operating Systems
  • Parallel Computing
  • Parallel Processing
  • Parallel Processors
  • Power Supplies
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  • Undersea Warfare
  • Universities
  • Warfare

Readers

  • Parallel and Distributed Computing.