A Reliability Study and Investigation of Complementary MOS/SOS integrated-Circuit Technology
Abstract
The objective of this study was an evaluation of the reliability and associated failure mechanisms of complementary MOS integrated circuits using silicon-on-sapphire technology. The results of this investigation indicate that, with appropriate screening, the self-aligned Si-gate CMOS/SOS technology can provide reliability equivalent to that of the Al-gate, bulk-silicon CMOS technology. The tests were conducted on CD4007 type inverter circuits processed in two different CMOS/SOS technologies: Al-gate and self-aligned Si-gate. The test program consisted of various combinations of electrical, thermal, and mechanical stresses designed to accelerate failure mechanisms. Extensive analysis was performed on the failed arrays, and predominant failure modes were determined. Activation energies for the predominant failure mechanisms were obtained, and results used for reliability predictions for both the Al-gate and the self-aligned Si-gate technologies. Recommendations for screening procedures for CMOS/SOS devices are also included. It must be pointed out that the statistics resulting from this investigation apply only to the processes used by the manufacturers, A and B, whose parts were used for the stress-testing program. There is no intent to imply that the statistical results of this program apply to devices made by other manufacturers with similar technologies.
Document Details
- Document Type
- Technical Report
- Publication Date
- Mar 01, 1977
- Accession Number
- ADB017987
Entities
People
- G. Caswell
- S. Cohen