Discrete Control Correction for Synchronizing Digital Networks.
Abstract
The patent application relates to a digital communications system having widely dispersed nodes transmitting between each other. A method and apparatus is described for synchronizing the processing of data at a node. Data transmitted between nodes is stored in speed buffers. The output of each buffer at a node is connected to the nodal processor and is controlled by the nodal clock. Synchronization is accomplished by performing a periodic adjustment of the frequency of the nodal clock. This adjustment is arrived at by sampling the buffer content of each node and extracting an error signal which represents the buffer position relative to the half full buffer position. The error signal is suitably weighted by a control and summed with all other weighted buffer error signals to produce a total error signal, which is added linearly to the original initial condition of the nodal clock and converted to an equivalent frequency.
Document Details
- Document Type
- Technical Report
- Publication Date
- Apr 24, 1975
- Accession Number
- ADD002951
Entities
People
- Harry A. Helm
- Maurice J. Raffensperger
- Raymond H. Bittel
Organizations
- United States Department of the Army