Precision Digital Sampler.
Abstract
The patent application describes a precision digital sampler which uses a sample rate clock providing pulses driving a tapped delay line where the total delay equals the PRI of the sample clock. The outputs of the tapped delay line are tied to a buffer register having a storage cell for each delay line tap. The data from the delay line is stored in the register on receipt of a command. In storing the outputs of the delay line, the state of the sample clock is known to the resolution of the taps. A decoder studies the states and the time for locating the leading edge of the sample clock is calculated. The calculated time is used by a control switching circuit to determine which tap should be enabled. The leading edge of the sample clock is thus enable at the resolution of the delay line taps.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jan 15, 1976
- Accession Number
- ADD003341
Entities
People
- John P. Belton
Organizations
- United States Department of the Air Force