Self-Aligned Recessed Gate with Low Source Resistance.
Abstract
A self-aligned recessed gate with low source resistance has an epitaxial structure with an n(+) contact layer. Source and drain contacts are put down, followed by resist spin-on and gate exposure. The gate channel is anodically thinned to expose the n active layer. The gate metal is evaporatively applied through the same resist opening which defines the gate channel. An insulating layer is laid down between the resist and the FET structure with ohmic contacts to prevent resist lifting, and a barrier layer is put over the ohmic contacts to provide insulating layer adhesion. The result is a sub-micron gate length FET having low source impedance. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- Jun 16, 1980
- Accession Number
- ADD008069
Entities
People
- Clifford Nishimoto
- Steve Gray Bandy
Organizations
- United States Department of the Navy