Multi Level Resist Technique for Lithography on Ceramic Substrates.
Abstract
A method for forming a microelectronic circuit and the microelectronic circuit produced by the method. A three level multiresist layer is deposited on the metal-coated surface of a substrate. The multiresist includes a thick polyimide layer, a thin metal layer, and a photo resist layer. A circuit pattern is formed in the photo resist layer and etched into the thin metal layer. The thin metal layer is utilized as a mask for plasma etching the circuit pattern into the thick polyimide layer and for exposing a region of the metal coating corresponding to the circuit pattern. A metallization is then formed by up-plating on the exposed metal coating. The resulting microelectronic circuit has very tight fabrication tolerances and includes a metallization with nearly vertical sidewalls.
Document Details
- Document Type
- Technical Report
- Publication Date
- Aug 19, 1983
- Accession Number
- ADD010582
Entities
People
- Martin C. Peckerar
- Steve S. Y. Mak
Organizations
- United States Department of the Navy