Accumulation-Mode in O.53 Ga 0.47 as Field Effect Transistor.
Abstract
The invention is a normally-off, accumulation mode field-effect-transistor (FET) utilizing a positive bias on an insulated gate to induce a conducting channel between source and drain ohmic contacts. The device is fabricated on an epitaxial layer of semi-insulating In(0.53)Ga(0.47)As. The semi-insulating layer of In(0.53)Ga(0.47)As is epitaxially deposited upon a semi-insulating InP substrate. Ohmic source and drain contacts are formed at separate regions upon the free surface of the semi-insulating In(0.53)Ga(0.47)As layer. Electrical connections to an external circuit are made to the ohmic source and drain contacts. A dielectric layer of either Si0(2) or Al(2)0(3) is deposited over the entire remaining surface of the In(0.53)Ga(0.47)As layer. A gate electrode is formed upon the dielectric insulating layer wherein said gate electrode extends up to the source and drain contacts so that the conducting channel formed by the accumulation layer would form a complete path from source to drain. The gate electrode also contains means to be electrically connected to an external electronic circuit. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- Oct 03, 1983
- Accession Number
- ADD010825
Entities
People
- D. Mullin
- H. H. Wieder
Organizations
- United States Department of the Navy