CMOS Devices Hardened Against Total Dose Radiation Effects
Abstract
A CMOS or NMOS device has one or more n-channel FETs disposed on a substrate, the device being resistant to total dose radiation failures, the device further including a negative voltage for applying a steady negative back bias to the substrate of the n-channel FETs to mitigate source, leakage currents in the device, thereby mitigating total dose radiation effects. A method for operating a CMOS or NMOS device to resist total dose radiation failures, the device having one or more n-channel FETs disposed on a substrate, has the steps: (a) disposing the CMOS or NMOS device in a radiation environment, the radiation environment delivering a dose on the order of tens or hundreds of krad (Si) over the period of use of the CMOS device; and (b) applying a negative back bias to the substrate of the NMOS FETs, at a voltage for mitigating leakage currents about the n-channel FETs.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jul 12, 2000
- Accession Number
- ADD019733
Entities
People
- Geoffrey Summers
Organizations
- United States Department of the Navy