Compact Filter Design
Abstract
An apparatus and method for signal detection in which a digital sample stream is fed round robin into a plurality of buffers, which are sequentially compared with a reference signal to determine a match. A processor determines the chronological order of the samples in each bit of each buffer, and directs a bitwise comparison between the signal in each buffer with the reference to determine a match, e.g., by correlation. The apparatus and method are preferably implemented with a Field- Programmable Gate Array (FPGA). This scheme permits real time correlation of a data stream with a reference without use of shift registers, or a significant number of dedicated logic blocks.
Document Details
- Document Type
- Technical Report
- Publication Date
- Sep 30, 2010
- Accession Number
- ADD020469
Entities
People
- Jeremy R. O'neal
Organizations
- Naval Undersea Warfare Center