Low Power 2-of-3-Valued CMOS Self-Checking Circuits,
Abstract
Two new schemes for the implementation of self-checking binary logic systems are proposed which utilizes low power 2-of-3-valued CMOS logic circuits. While 2-of-3-valued circuits are inherently ternary, only two of their three logic values are used in normal operation. The third (middle) logic value is used for self-checking and testing. To evaluate these circuits an open-short-conducting fault model for CMOS circuits is developed. All of the single faults in these circuits are studied and classified into four types, named mid-seeking, quasi-mid-seeking, mid-rejecting, and masked. The conclusions reached for 2-of-3-valued circuits in previous papers apply to these new circuits as well. Finally a comparison between implementation schemes is made on the basis of the size of the fault set each produces. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- May 01, 1983
- Accession Number
- ADP002334
Entities
People
- H. T. Mouftah
- K. C. Smith
- Miao Hu