A Quaternary Logic Encoder-Decoder Circuit Design Using CMOS,

Abstract

A binary-to-quaternary encoder and quaternary-to-binary decoder circuit pair is described as designed in a 5-volt CMOS technology. These circuits communicate with logical currents. Using model parameter values for a standard 5-micron polysilicon gate process technology and 10 microamp logical currents, we have simulated propagation delays of about 20 ns from binary encoder input to binary decoder output. With the encoder using scaled-up logical currents and driving a 100 pF load on the decoder input to simulate communication between chips, we observe simulated worst-case delays of about 35ns. (Author)

Document Details

Document Type
Technical Report
Publication Date
May 01, 1983
Accession Number
ADP002351

Entities

People

  • D. A. Freitas
  • K. W. Current

Organizations

  • University of California, Davis

Tags

Communities of Interest

  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Standards

Readers

  • Computer Programming and Software Development.
  • Electronics Engineering
  • Integrated Circuit Design and Technology.