Some Device Count Comparisons for Reduced Control Stores Using Multiple-Valued MOS (Metal-Oxide Semiconductor) Circuits,
Abstract
The design of decoders for multiple-valued MOS read-only memories (ROMs) used for reducing chip area in microprogrammed digital processors is considered. Using the threshold detection circuitry implemented by Intel Corporation, we present designs for one-out-of-four, one-out-of-sixteen, and one-out-of-thirty-two decoders for use with optimal radix four encodings of the microoperations in control stores, thus providing single layer decoding of the microoperations at the ROM outputs. We also include discussion of a design for a one-out-of-eight decoder for octal ROM cells. We use a newly obtained radix four optimal grouping of microoperations for the 256 word, 75 microoperation control store example derived from the control store of a Digital Equipment Corporation PDP-11/40 central processing unit to illustrate device counts obtainable, and we compare these counts to the two layer decoding scheme obtained by using a k-bits per cell encoding with 2k-to-binary code translation. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- May 01, 1983
- Accession Number
- ADP002361
Entities
People
- C. B. Silio Jr
- J. H. Pugsley
Organizations
- University of Maryland