A Method of Test Generation for Verification of Wiring Correctness,

Abstract

The paper presents a method of test generation for any multiterminal wiring network, such as printed circuit board, computer backpanel wiring etc. The method is based on the minimization of the test generated by examining the correct network with computer-controlled tester. Three-valued algebra was used. In comparison with more straightforward algorithm based on the adjacency matrix, lower space complexity has been achieved - O(n) rather than O(sq. n). (Author)

Document Details

Document Type
Technical Report
Publication Date
May 01, 1983
Accession Number
ADP002376

Entities

People

  • K. Bucholc

Tags

DTIC Thesaurus Topics

  • Algorithms
  • Circuit Boards
  • Circuits
  • Computers
  • Demographic Cohorts
  • Electronic Equipment
  • Networks
  • Printed Circuit Boards
  • Printed Circuits
  • Verification

Fields of Study

  • Computer science

Readers

  • Aerospace Test and Evaluation
  • Computer Engineering
  • Mathematical Modeling and Probability Theory.

Technology Areas

  • Space
  • Space - Satellites