Frequency (Standard) Combiner Selector,
Abstract
This paper discusses in detail the design of the FCS and how its functions are implemented by the various subsystems. The heart of the FCS is a digitally implemented phase lock loop based on a multiple mixer phase comparison system, a digitally controlled VXCO, and a microprocessor. The digital loop allows one to phase lock the VXCO to the average phase of the ensemble of standards even though the various standards operate at different frequencies and even though the VXCO output frequency is purposely offset from the average frequency of the ensemble. This offsetability feature allows the FCS to use a second very long time constant (1 week) phase lock loop to adjust the offset frequency so the timing system output is kept on time and on frequency with respect to a 1 pps Universal Coordinated Time (UTC) reference provided by a suitable timing receiver. The second loop also allows the microprocessor to determine the frequencies of individual input standards against UTC.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jan 01, 1983
- Accession Number
- ADP002460
Entities
People
- R. J. Costlow
- V. S. Reinhardt