Yield Enhancement by Fault Tolerant Systolic Arrays,

Abstract

In this paper interstitial fault tolerance (IFT), a technique for incorporating fault tolerance into systolic arrays in a natural manner, is discussed. IFT can be used for reliable computation or for yield enhancement. Here the author compares IFT used for yield enhancement to Wafer Scale Integration (WSI) techniques. Previous WIS techniques for yield enhancement have been proposed only for linear processing element arrays. IFT is effective for both linear and two dimensional arrays. Results of Monte Carlo yield simulation of IFT are presented. (Author)

Document Details

Document Type
Technical Report
Publication Date
Jan 01, 1983
Accession Number
ADP002620

Entities

People

  • R. H. Kuhn

Organizations

  • Northwestern University

Tags

DTIC Thesaurus Topics

  • California
  • Computations
  • Fault Tolerance
  • Large Scale Integration
  • Signal Processing
  • Simulations
  • Two Dimensional
  • Universities
  • Very Large Scale Integration
  • Workshops

Fields of Study

  • Engineering

Readers

  • Applied Combinatorial Optimization and Logic Circuit Design.
  • Computational Modeling and Simulation
  • Integrated Circuit Design and Technology.