Architectural and Control Considerations for a High Speed Signal Processor Implemented with an Ada (Trademark) Executive,
Abstract
A common assumption in the design of digital signal processors is that the critical system resource is the raw multiplication rate of the Arithmetic Element (AE). Currently, the architecture of these processors is based upon a distributed control network with the number of AEs required to meet the computational load of the application. Simulation of this type of system has shown that the actual bottleneck is the depth and complexity of the control network. This paper examines a signal processor architecture and an Ada executive control structure which supports a dataflow language. This architecture and control structures have been tested in a component level simulation. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- Nov 01, 1982
- Accession Number
- ADP003594
Entities
People
- S. E. Adams
- T. R. Butler