An Embedded Fusion Processor
Abstract
This paper describes an embedded High Performance Computer (HPC) designed to perform the sensor data fusion for the Discriminating Interceptor Technology Program (DITP). The HPC's electrical and physical architecture will be reviewed, The processor's architecture, FPASP5, evolved from years of Ballistic Missile Defense Organization (BMDO), and US Air Force research into wafer scale packaging and power efficient programmable signal processors for space-based applications. The processors, memory, and interface bare chips are packaged in Multichip Modules (MCMs). Our current version is designated MCM3. These MCMs can be stacked in thin layers before being inserted into the chassis level interconnect scheme The chassis interconnect leverages a BMDO and Air Force Research Laboratory (AFRL) funded technology called Highly Integrated Packaging and Processing (HIPP). HIPP allows MCMs and two by two inch Printed Circuit Boards (PCBs) to be stacked together and interconnected with printed flexible flaps and a micro backplane. The combination of these techniques allows us to meet the strict constraints of space based surveillance and interceptor applications.
Document Details
- Document Type
- Technical Report
- Publication Date
- Oct 01, 2000
- Accession Number
- ADP010841
Entities
People
- John Rooks
Organizations
- Air Force Research Laboratory