Avoiding Obsolescence with a Low Cost Scalable Fault-Tolerant Computer Architecture

Abstract

This new computer architecture can use anything from COTS (Commercial Off-The-Shelf) microcontrollers to the latest high-end processors. It is a distributed fault-tolerant architecture that is dynamically reconfigurable in the event of device failures and is fully programmable in conventional high level languages. By using a simple two-level hierarchy with redundant control processors that configure the I/O (Input/Output) processor arrangement even the failure of several processors will have no effect on data. An example is given of a real-time data acquisition system with a total cost for a 16 channel device with mixed sync/async and proprietary baud rates of less than $500 in parts. This example system can be reconfigured to any arrangement of 16 or less serial interfaces.

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Document Details

Document Type
Technical Report
Publication Date
Oct 01, 2000
Accession Number
ADP010975

Entities

People

  • Josef Schaff

Organizations

  • Naval Air Systems Command

Tags

Communities of Interest

  • Advanced Electronics
  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Central Processing Units
  • Commerce
  • Computer Architecture
  • Computer Programming
  • Computer Programs
  • Computers
  • Computing System Architectures
  • Data Acquisition
  • Failure Mode And Effect Analysis
  • Kernels (Operating System)
  • Language
  • Networks
  • Operating Systems
  • Processing Equipment
  • Signal Processing
  • Simulations
  • Standards

Readers

  • Computer Science/Computer Engineering/Data Science/Digital Signal Processing.
  • Parallel and Distributed Computing.