Exploiting HHPC for Parallel Discrete Event Simulation
Abstract
Parallel Discrete Event Simulation (PDES) is an important application in use in many DoD projects; for example, PDES is used in large-scale war-gaming, and in complex system design, analysis and verification. Improving PDES performance and capacity allows faster simulation times and more extensive analysis of more detailed models. These benefits are not application-specific: they should reflect any application that uses the improved simulation kernel. In this work we overview our efforts for optimizing PDES in a Heterogeneous High Performance Computing (HHPC) environment. We profile the SPEEDES simulator and identify several opportunities. We report on our experiences on two fronts: (1) optimizing the communication subsystem -- a critical system for PDES since it is a fine-grained application and (2) exploring the use of augmented FPGA boards to accelerate simulation. While such approaches have been attempted for sequential and data path intensive applications, we believe that their use in clustered environments is novel. Both efforts are works in progress; we present our designs and some preliminary analysis results. For example, removing the centralized communication server from event message exchange path with a number of other small improvements to the simulation cycle, improved performance by an average of 20% performance improvement for one of our large benchmarks.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jun 01, 2004
- Accession Number
- ADP023855
Entities
People
- James Hanna
- Nael Abu-ghazaleh
- Richard Linderman
- Robert Hillman
Organizations
- Binghamton University