Power/Area-Efficient I/O and Write Circuits for Memristor Crossbar Array-Based Neuromorphic Computing System
Abstract
The overarching research goal is to develop a high-efficiency neuromorphic computing system based on the recently-developed memristor crossbar array technology. While the primary research effort focuses on the system-level implementation and the operating algorithms, the system’s input and output (I/O) and write circuits have not been systematically optimized to achieve high computation efficiency with minimal chip area and power consumption. The research objectives of this project are to design and test power/area-efficient I/O and write circuits used in the memristor crossbar array-based neuromorphic computing system, and seamlessly integrate them with the rest of the system to demonstrate a high-efficiency neuromorphic computer.
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Feb 11, 2016
- Source ID
- FA87501510069
Entities
People
- Hao Jiang
Organizations
- Rome Laboratory
- San Francisco State University
- United States Air Force