Agile 3D Memory Interfaces
Abstract
The Tezzaron DiRAM4 3D memory offers potential for a fast memory with a very high IO bandwidth. Integrating it with a processor on an interposer, or via a redistribution layer, will lead to a “breakdown” of the traditional memory wall between processors and dynamic memory, in turn offering significant potential for a dramatic improvement in performance per unit of power. NCSU proposes to research and prototype 3D memory controller designs. NCSU will present its prototype memory controller design in three cycles. The first cycle will consist of a basic memory controller design for processing architectures. In the second cycle, NCSU will evaluate the basic design and revise any design features that need to be addressed or corrected and additionally create a modular interface for integrating their design to a 3D memory such as the Tezzaron DiRAM4 memory. In the third cycle, NCSU will modify the prototype in an effort to demonstrate the DiRAM4 memory acting as a level 2 cache for general purpose processing architectures. A memory model of NCSU’s prototype memory controller will be developed to help processor designers understand what they will have to do when developing their own controller and for functional verification. Concurrently, NCSU will conduct a design study exploring routability of different interposer and redistribution layer options.
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Feb 11, 2016
- Source ID
- FA87501510280
Entities
People
- Paul D Franzon
Organizations
- North Carolina State University
- Rome Laboratory
- United States Air Force