FABRICATION OF A MEMRISTIVE DYNAMIC ADAPTIVE NEURAL NETWORK ARRAY (mrDANNA)
Abstract
The research proposed here aims to enable future generations of computing systems by (1) leveraging an emerging, power-efficient device technology (i.e. the memristor) and (2) considering an alternative architectural model (i.e. neuromorphic) that promises to overcome many of the performance limitations of conventional von Neumann systems. The specific neuromorphic architecture on which the proposed mrDANNA is based is the Neuroscience-Inspired Dynamic Architecture (NIDA), developed by researchers at the University of Tennessee, Knoxville (UTK) as an approach to applying neuromorphic principles to a wide variety of applications. Key features of the NIDA architecture include: (1) a spiky representation of data, (2) the ability for the system to adapt during run-time, and (3) a synaptic representation including delay distance as well as weight information. The structure and simplicity of the NIDA architectural model has recently been leveraged in the development of a Dynamic Adaptive Neural Network Array (DANNA), an efficient digital system constructed from a basic element that can be configured to represent either a neuron or a synapse. For the proposed research project we will leverage the features of the NIDA architecture in the construction of a mixed-mode, analog/digital memristor-based DANNA (mrDANNA) system. The proposed mrDANNA will maintain several important features of the digital representation of DANNA, including real-time dynamic adaptability and synaptic functionality that includes both weight and delay distance information. This project will leverage a hybrid CMOS/Memristor process developed and tested at the SUNY Polytechnic Institute’s College of Nanoscale Science and Engineering (CNSE) in the production of a test chip and first generation prototype of the mrDANNA system. The process integrates metal-oxide memristors in the metal layers of a 65 nm CMOS process, leading to a seamless CMOS/Memristor integration process. In the early stages of the proposed work, material stacks will be considered and modeled with the intent of tailoring memristor devices for the mrDANNA system. The two teams from UTK and CNSE will collaborate on the physical design of test circuits and a prototype mrDANNA array with the final test chip design fabricated at CNSE.
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Feb 29, 2016
- Source ID
- FA87501610063
Entities
People
- Nathaniel C Cady
Organizations
- Research Foundation for the State University of New York
- Rome Laboratory
- United States Air Force