Design of a Memristive Dynamic Adaptive Neural Network Array (mrDanna)
Abstract
For the proposed research project we will leverage the features of the Neuroscience-Inspired Dynamic Architecture in the construction of a mixed-mode, analog/digital memristor-based Dynamic Adaptive Neural Network Array (mrDANNA) system. The proposed mrDANNA will maintain several important features of the digital representation of DANNA, including real-time dynamic adaptability and synaptic functionality that includes both weight and delay distance information. The proposed mrDANNA system will improve performance and power consumption by leveraging memristor technology for analog operation and increased device density. NIDA/DANNA has already been shown to support control applications (solving the pole balancing problem) and classification (handwritten character recognition and the Wisconsin Cancer database). The proposed mrDANNA system will be tested against similar applications as those used to verify the digital DANNA implementation. Applications to be considered for further testing are defined by spatio-temporal data, such as: video and audio classification, autonomous control of robotic systems, and real-time anomaly detection in network traffic. In order to streamline the configuration and validation of the mrDANNA system, a software toolset is to be developed that will be used to verify the system using common benchmarking tests, such as handwritten character recognition. A simulation framework will be developed as part of the software toolset used to simulate, initialize and test the mrDANNA system. This project will leverage a hybrid CMOS/Memristor process developed and tested at the SUNY Polytechnic Institute’s College of Nanoscale Science and Engineering (CNSE) in the production of a test chip and first generation prototype of the mrDANNA system. The process integrates metal-oxide memristors in the metal layers of the 65 nm 10LPe CMOS process from IBM, leading to a seamless CMOS/Memristor integration process. In the early stages of the proposed work, material stacks will be considered and modeled with the intent of tailoring memristor devices for the mrDANNA system. The two teams from UTK and CNSE will collaborate on the physical design of test circuits and a prototype mrDANNA array with the final test chip design fabricated at CNSE.
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Mar 04, 2016
- Source ID
- FA87501610065
Entities
People
- Garret S. Rose
Organizations
- Rome Laboratory
- United States Air Force
- University of Tennessee