32nm Hafnium (IV) Oxide (HfO2) Negative Metal Oxide Semiconductor (NMOS) Electrically Erasable
Abstract
The goal of this program is to research and develop Electrically Erasable Programmable Read-Only Memory (EEPROM) intellectual property (IP) base on silicon dioxide/Hafnium (IV) oxide (SiO2/HfO2) gate 32 nanometer (nm) Complementary Metal-Oxide-Semiconductor (CMOS). SiO2/HfO2 gate 32nm CMOS is known to be at risk for long term threshold shifts due to charge trapping. To this end, 32 and 22nm CMOS Silicon on Insulator (SOI) processes have been proposed by others as potential EEPROM memory IP. This research and development effort will develop (1) stochastic based write-erase threshold shift models, (2) write and erase protocols, i.e. voltages and duration, (3) retention rates, including read-write error rates, and (4) multiple EEPROM architecture IP. It is anticipated that the outcomes of this project will aid in the deployment of in situ EEPROM IP for silicon architectures for any division that employs trusted foundry fabrication capabilities.
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Jan 13, 2017
- Source ID
- FA87501710057
Entities
People
- Chris Hutchens
Organizations
- Oklahoma State University–Stillwater
- Rome Laboratory
- United States Air Force