Optimization and Exploration of Trusted Low-Power High Performance Computer Architectures
Abstract
The Recipient will seek to research and develop high-level synthesis tools for System on Chip (SoC) platforms in nanometer CMOS technologies that (1) provide the ability to efficiently integrate embedded memories, low-power/high-performance circuits and processors, mixed-signal designs, and communication structures, (2) combine synthesis and layout information to accurately estimate area, delay, and power from high-level SoC architecture descriptions, and (3) facilitate rapid design-space exploration of secure SoC solutions.
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Sep 13, 2017
- Source ID
- FA87501710261
Entities
People
- James Stine
Organizations
- Oklahoma State University–Stillwater
- Rome Laboratory
- United States Air Force