Demonstration of Rapid Design Techniques in Advanced Technologies
Abstract
Custom, application-optimized integrated circuits are key enablers for a wide variety of commercial as well as government systems, but rising design complexity, fabrication costs, and levels of integration (of both digital and analog/mixed-signal content) have led to excessively high design time and/or NRE. The issue is particularly acute in applications with relatively low final volumes with significantly less opportunity to amortize/recoup initial design costs. In order to begin addressing this issue, for this seedling effort we propose to demonstrate the integration and application of two designer productivity enhancement frameworks presently under development at Berkeley: Constructing Hardware in Scala Embedded Language (Chisel) as the vehicle for both the description/generation of digital components as well as top-level integration, and the Berkeley Analog Generator (BAG) for generation of analog, mixed-signal and RF building blocks. In order to highlight their utility, these frameworks will be adapted to a FinFET based 14/16-nm CMOS process and used to generate complete designs (i.e., schematics + DRC/LVS clean layouts) of mixed-signal SoC building blocks, and in particular, SAR ADCs integrated with a digital baseband for communications applications (particularly for array applications). To prove the quality of the designs generated in this manner, they will be fabricated on a test-chip and subsequently measured and characterized to compare their specifications against those predicted by the generators. The main premise of this project is that the use of function generators (as opposed to function instances) combined with higher levels of design abstraction improve design efficiency and foster re-use. Since these generators include unit tests which will be automatically checked on each instance produced by the generator, design verification is accelerated as well. By enabling rapid mapping to silicon – where this mapping is either inherently performed by the generator itself (in BAG for analog/mixed-signal blocks) or by elaborating the behavioral description into a physical design using additional tools (e.g.., running an instance’s Verilog produced by Chisel through synthesis/place and route) – this approach further enables design-space exploration for optimal efficiency. The entire design is managed by using repositories, and in structure resembles the development process of a large software project.
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Feb 11, 2016
- Source ID
- HR00111510010
Entities
People
- Elad Alon
Organizations
- Defense Advanced Research Projects Agency
- University of California Regents