Demonstration of 14nm Patterning and Construct-Based Design Methodology for Efficient Time-to-Mission
Abstract
As the scaling of CMOS integrated circuit technologies reaches the 14nm node, the time required to complete design closure increases dramatically due to the challenges of the nanoscale physics. This design complexity creates time-to-mission uncertainty for the integrated circuit product, which causes DoD contractors to revert to mature CMOS technologies that are more predictable, but offer inferior performance. This project proposes to demonstrate a 14nm construct-based design flow, built on commercially available design tools, that facilitates efficient design at a modest trade-off of silicon area. First, design rules, which have historically served as a design manufacturing interface, are failing to robustly capture the underlying manufacturing process, and must be now augmented by prescriptive layout pattern constructs. This project will develop methods to facilitate specification of the allowable patterns, rather than complex design rules that describe the disallowed constructs. Secondly, embedded memories (SRAM blocks) are critical components of all digital and SoC designs, and their scaling from one technology node to the next has been severely limited by manufacturing process variations. A significant benefit of the construct-based design patterning is that it can make the “compilation” of SRAM blocks much more efficient and effective. This work will demonstrate how the prescriptive pattern constructs can used to create SRAM blocks that are scalable, manufacturable, customizable, verifiable, and efficient. Lastly, analog components often represent the design bottleneck for many system-on-chip designs, and the 14nm technology node creates new challenges for their implementation. The FinFET devices that have replaced MOSFETs at the 14nm node require analog transistor sizing to work with discretized widths based on fin height, and a very limited number of transistor lengths (fin thicknesses). This creates a need for capture and reuse of analog primitives at a slightly higher level of abstraction than what is done presently. This project will explore the creation of an xCell (extracted construct cell) that can be scripted for a range of layout options, to facilitate efficient design and layout of analog components. In aggregate, this project will form the basis of what can become a complete construct-based design methodology that is based on prescriptive constructs for creating fabrics and encapsulating the designs that can be mapped onto them.
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Feb 11, 2016
- Source ID
- HR00111510011
Entities
People
- Larry Pileggi
Organizations
- Defense Advanced Research Projects Agency
- Massachusetts Institute of Technology