Silicon Photonics enabled Reconfigurable Optical Analog Processor (SiROAP)
Abstract
There is a growing trend of application-specific photonic ICs (PICs) for signal processing. However, PIC designers undertake long design cycles involving simulation, layout, fabrication, and testing, thus incurring significant labor and development cost. A reconfigurable general-purpose PIC will allow for rapid design exploration and revolutionize RF photonic systems in a manner similar to the impact that field-programmable gate arrays (FPGAs) have on electronics. Recently, tunable SiP processors using square and hexagonal meshes have been demonstrated to realize a range of reconfigurable optical circuits. These processors were reconfigured, resulting in a variety of Mach-Zehnder Interferometer (MZI) and coupled ring structures. However, these were small-scale PICs, fabricated using a passive silicon nitride platform, or using e-beam lithography, and resulted in 20 distinct functionalities. These architectures have limited scalability and have not employed active photonics to realize functionalities other than passive optical filters. To take reconfigurable PICs beyond small-scale homogeneous photonic circuits, this program seeks to develop a large-scale reconfigurable SiP-enabled, reconfigurable optical analog processor (SiROAP) that allows passive as well as active reconfigurable photonic components in a hierarchical architecture, similar to contemporary FPGAs. Specifically, SiROAP will be comprised of an array of configurable optical blocks, which will be realized using reconfigurable optical meshes, forming programmable connections with the couplers and programmable connections to other on-chip resources, such as the delay lines and detectors. The increased degrees of freedom will allow for rapid prototyping of numerous analog photonic signal processing scenarios by combining linearized RF-to-optical (EO) modulation, optical-domain signal processing, and high-speed detection. A software tool will be developed to synthesize user design specifications to perform simulation-based design optimization. The approach planned for this project addresses the scalability of complex reconfigurable PICs, but also extends it to active RF photonic functionalities, and includes synergistic integration of electronics, photonics and algorithms for automatic synthesis and tuning. The goal is to develop a large-scale reconfigurable optical analog processor architecture and a synthesis tool that will enable a wide-range of RF signal processing applications, using silicon photonics (SiP) technology. The planned architecture and the software tool will revolutionize the semiconductor, photonics, and wireless industries. The hierarchical architecture will allow for scaling to very large reconfigurable PICs. Electronics-enabled reconfigurability will allow feedback loops to set and maintain desired circuit response and also allow novel capabilities, such as linearization of RF-to-optical modulators and in-situ tuning of filters; not addressed in prior work. Software-defined reconfiguration of active and passive optical meshes will enable exploration of entirely new ideas leading to system-level innovation.
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Jan 14, 2022
- Source ID
- HR00112110001
Entities
People
- Vishal Saxena
Organizations
- Defense Advanced Research Projects Agency
- University of Delaware