Broadband Spectrum Channelizing Receiver Architectures with Interference Supression and Sub-Band Attenuation Capability
Abstract
Broadband spectrum channelizers can serve as enablers for new systems and applications for communications, signal analysis and signal detection. In the proposed research, we will investigate the design and analysis of power-efficient and spectrum-agile analog and mixed-signal broadband channelizers that can span bandwidths of several GHz. The designs will seek to address fundamental performance limitations of current approaches to spectrum channelization, and digitization of broadband signals. The channelizer architectures considered here will utilize frequency-synthesis capable harmonicrejection downconversion techniques. These downconverters can internally synthesize multiple downconversion frequencies while using a single fixed-frequency synthesizer. The channelizers will allow for full or partial spectrum selection, with power scaling capability. Analog and mixed-signal architectures will be considered. Power dissipation requirements for these approaches for achieving a given dynamic range will be analyzed. Degradation mechanisms that limit the performance of the channelizers, and circuit and architectural techniques for mitigation of these will be studied. The designs will be benchmarked relative to broadband ADC-based approaches and fundamental similarities and dissimilarities in performance will be investigated. A second part of the effort will focus on the analysis and design of tunable active sub-band and interference rejection techniques, as applied to the channelizer. These will be based on the use of frequency-translated feedback and feedforward approaches. These techniques will be utilized to maximize the dynamic range across the entire bandwidth. A broadband channelizer that combines the above mentioned aspects will be implemented. For an initial representative design, we will target a frequency range from DC to 3 GHz. The dynamic range will be specified to be in excess of that for commercial long-range wireless communication standards, such as cellular phone systems. The designs will be validated in a deep-submicron CMOS technology.
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Aug 12, 2016
- Source ID
- N000141512097
Entities
People
- Ranjit Gharpurey
Organizations
- Office of Naval Research
- United States Navy
- University of Texas at Austin