Reliability Prediction of Wide Band-Gap Semiconductor Power Devices
Abstract
Reliability Prediction of Wide Band-Gap Semiconductor Power Devices Joseph B. Bernstein Professor, Department of Electrical Engineering Faculty of Engineering, Ariel University, Israel +972-(0)52-575-9301, Josephbe@ariel.ac.il Historically and up to the present time, the reliability of our most sophisticated electronic systems are calculated based on the assumption of one (dominant) failure mechanism. The failure rate is generally determined from published handbook values that are based on accelerated life-tests where zero failures were found. The failure rate is reported as a constant time-independent probability, known as “Failure In Time” (FIT). The FIT value that a manufacturer reports is mathematically the inverse of the mean time-to-fail (MTTF) times 109 failures per part-hour. Today, there is no qualification standard that accepts failures. Thus, the reported FIT is invariably based on a zero-failure result from a tailored accelerated life test. The test is based on what is assumed to be the dominant failure mechanism, but this is never verified since there were no failures to analyze. The result of this “single potential mechanism” accelerated test (that never caused a failure to occur) results in a misleading assessment of the reliability when multiple mechanisms exist. This contradiction is recognized in the most recent JEDEC Publication JEP 122G Rev. Oct. 2011, that states: “When multiple failure mechanisms and thus multiple acceleration factors are involved, then a proper summation technique, e.g., sum-ofthe- failure rates method, is required.” However, neither this standard nor any other handbook suggests what exactly is a “proper summation technique.” Furthermore, newly introduced wide bandgap semiconductor power devices are well known to exhibit more than a single failure mechanism. Over the course of nearly 10 years, our research group has investigated hot carrier injection, time-dependent dielectric breakdown, single-event gate rupture, electromigration, avalanching and current crowding effects in SiC power devices as well as Silicon IGBTs. Our research confirms that these mechanisms as well as solder, packaging and other thermal related failures can result in failures of newly developed power devices. We propose to apply our linear approach to predictive reliability assessment incorporating our Multiple High Temperature Overstress Lifetest (M-HTOL) for newly developed wide band-gap semiconductor devices. We will evaluate calculating FIT based on the time-independent (Poisson) statistics, assuming a combination of known and yet-to-be analyzed failure mechanisms. Our goal is experimentally to investigate the failure mechanisms that are understood to occur in SiC and GaN power devices and develop their physics of failure models with the goal of predicting the actual reliability based on the system environment. It is our intent to show that the era of confidence in reliability prediction has arrived and that we can make reasonable reliability predictions from qualification testing at the system level.
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Aug 08, 2016
- Source ID
- N000141512159
Entities
People
- Joseph Bernstein
Organizations
- Ariel University
- Office of Naval Research
- United States Navy