Trusted Fabrication through 3D Integration
Abstract
NCSU will conduct a study on the feasibility of doing trusted chip fabrication using an untrusted CMOS source and a trusted 3D integration fab. A CAD tool flow is used to design two CMOS tiers together with a wiring only tier. This creates a three wafer stack that can be integrated using established 3D processes. During the study, we will assemble the CAD flow and then run a set of different designs through the flow for different technology nodes. Obfuscation will be measured through suitable metrics and red-teaming to be done at Raytheon BBN.
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Aug 12, 2016
- Source ID
- N000141512758
Entities
People
- Paul D Franzon
Organizations
- North Carolina State University
- Office of Naval Research
- United States Navy