Heterogeneous IP Ecosystem enabling Reuse
Abstract
Statement of WorkTask 1 – Preliminary study of cost model, tool flows, and methodology:Months 1-3:1.1 Develop preliminary cost model for heterogeneous IP integration, interconnect, and foundry services1.2 Characterize the scope of tool flow activities needed for making heterogeneous IP integrationas seamless as possible1.3 Describe methodology needed to enable a holistic heterogeneous IP reuse ecosystem1.4 Deliver report detailing preliminary findings and program plan for more detailed 6-month study in Task 2 - Analysis of current tool barriers to heterogeneous IP integration:Months 4-9:2.1 Identify candidate designs and demonstrate application of cost model and refine cost model based on the outcome2.2 Identify and describe characteristics needed for PDKs and other supporting files to realize the tool flow needed to support the HIER model2.3 Develop a concept of operations for the HIER model to provide further detail on the methodology initiated in Task 1.32.4 Deliver final report detailing all findings and including concept of operations for HIERApproachThe effort will focus on analyzing the current process and tools shortcomings in heterogeneous IP integration and propose and evaluate the concept of operations for achieving a functioning infrastructure for heterogeneous IP reuse. The proposed project therefore includes the following technical task thrusts: (1) Development of a cost model for heterogeneous IP integration,interconnect, and foundry services (2) Development of tool flows enabling seamless heterogeneous IP integration; and (3) Devising a methodology detailing a concept of operations to achieve a heterogeneous IP reuse infrastructure.ObjectiveFormulate the detailed requirements for accomplishing a successful Heterogeneous IP Ecosystem enabling Reuse (HIER), including chip fabrication process issues, tools, methodologies, concept of operations, and a cost model for achieving a functioning infrastructure for heterogeneous IP reuse.Overall Merit and ONR Mission/Relevance:The proposed work could enable DoD-specific IP reuse and would be relevant to a variety of programs within the Command, Control, Communications, Computers, Intelligence, Surveillance and Reconnaissance (C4ISR) Department at ONR. Dr. Draper (PI) is well qualified for this effort, having led the micro-architecture and/or VLSI effort on several large projects in the past 15 years, including many DARPA-sponsored programs such as Integrity and Reliability in Integrated Circuits, Ubiquitous High-Performance Computing, Trust in Integrated Circuits, Radiation Hardening by Design, Polymorphous Computing Architectures, and Data-Intensive Systems.Additional Info:Funded by DARPA (Dan Green)Full funding ($405,000) expected via DARPA MIPR.
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Sep 21, 2018
- Source ID
- N000141612039
Entities
People
- Jeffrey Draper
Organizations
- Office of Naval Research
- United States Navy
- University of Southern California